Freescale Semiconductor /MK21D5WS /UART2 /PFIFO

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Interpret as PFIFO

RXFIFOSIZE=000, TXFE=0, TXFIFOSIZE=000, RXFE=0

Description

UART FIFO Parameters

Fields

RXFIFOSIZE	Receive FIFO. Buffer Depth 0 (000): Receive FIFO/Buffer depth = 1 dataword. 1 (001): Receive FIFO/Buffer depth = 4 datawords. 2 (010): Receive FIFO/Buffer depth = 8 datawords. 3 (011): Receive FIFO/Buffer depth = 16 datawords. 4 (100): Receive FIFO/Buffer depth = 32 datawords. 5 (101): Receive FIFO/Buffer depth = 64 datawords. 6 (110): Receive FIFO/Buffer depth = 128 datawords. 7 (111): Reserved.
RXFE	Receive FIFO Enable 0 (0): Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 1 (1): Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
TXFIFOSIZE	Transmit FIFO. Buffer Depth 0 (000): Transmit FIFO/Buffer depth = 1 dataword. 1 (001): Transmit FIFO/Buffer depth = 4 datawords. 2 (010): Transmit FIFO/Buffer depth = 8 datawords. 3 (011): Transmit FIFO/Buffer depth = 16 datawords. 4 (100): Transmit FIFO/Buffer depth = 32 datawords. 5 (101): Transmit FIFO/Buffer depth = 64 datawords. 6 (110): Transmit FIFO/Buffer depth = 128 datawords. 7 (111): Reserved.
TXFE	Transmit FIFO Enable 0 (0): Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 1 (1): Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.

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